Modern processor systems have placed increasing demands over the bandwidth and capacity on the main memory; as a result, power consumption by the main memory has been growing and accounting for a significant portion of the overall system power usage.
A typical main memory is composed of a volatile memory such as the dynamic random-access memory (DRAM). A volatile memory loses its data quickly when its power supply is removed. A DRAM not only needs a constant power supply to retain data, but its memory cells also need to be periodically refreshed. A DRAM stores each data bit in a capacitor that can be either charged or discharged; these two states are taken to represent the two values (i.e., 0 and 1) of a bit. A charged capacitor slowly leaks over time. Thus, the capacitors are refreshed periodically to replenish the charges such that the stored information can be retained.
Synchronous dynamic random-access memory (SDRAM) is a DRAM device where the operation of its external pin interface is coordinated by an externally supplied clock signal. Some widely adopted SDRAM in modern computing systems include a family of double data rate random-access memory, such as DDR1, DDR2, DDR3 and DDR4.
In a typical scenario, the refresh operations of a DRAM device is managed by a controller, which issues auto-refresh commands at a specified rate to refresh a certain number of rows in each memory chip. Normal memory operations resume after the completion of an auto-refresh. Auto-refresh dissipates substantial power since background power is consumed by the delay locked loop (DLL) and peripheral logic in addition to the power required for refresh. To save background power, a DRAM device has an option to enter a self-refresh mode, where the device internally generates refresh pulses using a built-in timer. In other words, when a device is in the self-refresh mode, all external I/O pins and clocks are disabled, the DLL is turned off, and the device preserves data without any intervention from the memory controller. Some DDR devices support a partial array self-refresh (PASR) option, where the controller can program the device to refresh only a certain portion of the memory.
Modern computing systems utilize the aforementioned power management techniques to reduce the power consumption. However, volatile memory devices still account for a growing percentage of power consumption in these computing systems. Therefore, there is a need to further limit the power consumption of a volatile memory.